The occurrence of errors and faults in the operation of digital electronic circuitry may be detected by the use of duplicated units running in parallel on identical input data along with circuitry which compares corresponding signals from the duplicate units. Such signal comparison circuits are often termed "matcher circuits" in digital processing technology. In order to utilize identical processing units and to provide independent error and fault output signals in each unit, matcher circuitry is provided in each of the duplicated processing units and the signals to be compared are cross-coupled between the duplicated units. The circuitry in a processing unit may comprise a full matcher circuit which generates inequality signals for all types of mismatch errors, i.e., A = "0" and B = "1", or A = "1" and B = "0", or, alternatively, the matcher circuitry in each unit comprises a half matcher circuit which generates a mismatch signal for only one of the two possible mismatch conditions. Where half matcher circuits are utilized, the half matcher in one unit detects one type of error, e.g., A = "1", B = "0"; while the half matcher in the other unit detects the other type of error, e.g., A = "0", B = "1". In any event, in such prior art circuitry whether full matcher or half matchers are utilized, the signals to be compared are cross-coupled between the duplicated units which requires two interconnecting wires for each pair of signals to be compared. It is an object of this invention to provide a pair of half matcher circuits interconnected by only a single wire thereby reducing the number of wires interconnecting the two duplicate units.